Intel’s EMIB Achieves 90% Yield as Analyst Predicts Foundry Success, EMIB-T Expected to Scale Beyond 12x Reticle by 2028

Intel’s EMIB (Embedded Multi-die Interconnect Bridge) technology has reached impressive yield rates, positioning it as a frontrunner for integration into future AI data center chips.

Intel EMIB: Pioneering Advanced Packaging Competitiveness Against TSMC

Recent discussions have spotlighted EMIB’s growing appeal among AI companies for their next-gen chip designs. The primary goal of this innovative technology is to present an efficient and scalable substitute for TSMC’s CoWoS (Chip-on-Wafer-on-Substrate) solutions.

Prominent players like Google plan to utilize Intel’s advanced packaging in their upcoming Tensor Processing Units (TPUs), while NVIDIA is also eyeing EMIB for its next-generation Feynman chips. In light of these developments, research analyst Jeff Pu from GF Securities Technology Research has shared optimistic insights about EMIB’s impressive trajectory.

Abstract of MediaTek (2454 TT) Earnings Note & Implications Following our report on March 25 (On Path to >NT$200 EPS) and April 27 (Two More Things!), MTK’s share price has risen by ~50%, and we expect it to react positively post today’s earnings. We raised TP to NT$3, 528…

— Jeff Pu (@sssjeffpu) April 30, 2026

Significantly, Jeff Pu noted that Intel’s EMIB technology has achieved a yield rate of 90%, a promising sign for Intel’s Foundry division and indicative of the trust in its capabilities. Meta is among the key names contemplating EMIB for future CPUs, although their project may not materialize until late 2028.

Continuous advancements showcase Intel’s emphasis on the array of benefits EMIB presents: enhanced yield efficiency, reduced power consumption, lower manufacturing costs, and the practicality of larger mixed-node systems.

An Intel presentation slide titled 'A True Packaging Breakthrough' — A comparison showcasing EMIB’s improved flexibility over traditional packaging methods.

A diagram contrasting 'Industry Standard' packaging with Intel's 'EMIB' — Highlighting EMIB’s advantages in yield, cost, and design.

A diagram showing 'The Industry Standard 2.5D Solution' — A visual representation emphasizing the complexity of traditional solutions.

A recent Intel video illustrates that EMIB yields are on par with FCBGA (Flip Chip Ball Grid Array), while providing greater die connection density. FCBGA, a prevalent high-performance packaging technology, connects different components directly to the PCB via solder bumps, unlike EMIB, which interlinks dies within its bridge.

Differentiating between EMIB-M and EMIB-T

At present, Intel offers two distinct variations of the EMIB technology: EMIB-M and EMIB-T. The EMIB-M variant prioritizes efficiency, incorporating Metal-Insulator-Metal (MIM) capacitors within its silicon bridge to bolster power delivery and minimize signal noise. While MIM capacitors are marginally more expensive than traditional Metal-Oxide-Metal counterparts, they provide enhanced stability and reduced leakage.

An illustration demonstrating 'EMIB-M Incorporates MIM Capacitors' — Detailing the incorporation of MIM capacitors to improve performance.

The construction of EMIB-M involves assembling high-density 3D structures through chiplets interconnected via the EMIB-M bridge, which ensures high-bandwidth communication. Power is directed around the bridge in this setup.

Efficient and cost-saving connection for multiple intricate die.
Utilizes 2.5D packaging style for logic-logic and high-bandwidth memory (HBM).
EMIB-M employs MIM capacitors, while EMIB-T incorporates Through-Silicon Vias (TSVs).
Silicon bridge seamlessly embedded in the package substrate for enhanced connectivity.
EMIB-T facilitates the integration of intellectual property from diverse packaging methodologies.
Streamlined supply chain and assembly processes enhance efficiency.
Proven in mass production since 2017, benefiting both Intel and external suppliers.

Conversely, EMIB-T optimizes power routing directly through the bridge, allowing greater density due to its integration of TSVs, which is particularly beneficial for high-performance AI chips.

A diagram illustrating Intel's EMIB-T technology — Showcasing the integration of TSVs for direct power and signal delivery.

Scaling EMIB for the Age of Hyperscalers

Current projections indicate that EMIB-T will support chip scalability exceeding 8x the reticle size within 120×120 packages, accommodating 12 HBM chips along with four compact chiplets and over 20 EMIB-T interconnections. By 2028, Intel aims to expand this to over 12x the reticle size in 120×180 packages, accommodating 24 HBM dies and more than 38 EMIB-T connections.

In comparison, TSMC forecasts achieving 14x reticle sizes by 2028 with up to 20 HBM packages. The company also plans to develop System of Wafer (SoW) packages for large-scale advanced chip packaging, albeit at a significantly higher cost compared to CoWoS.

A primary strength of EMIB is its agnostic nature towards IP and chip process nodes, enabling versatile integration of various chips from different providers, while ensuring optimal performance in terms of bandwidth and power efficiency.

https://www.youtube.com/watch?v=O5i9JehZF8Y

Intel EMIB II | Intel Foundry (https://www.youtube.com/watch?v=O5i9JehZF8Y)

Source & Images