Understanding the AI Chip Supply Chain: How NVIDIA and Others Depend on a Complex Network of Companies for Chip Production

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The remarkable growth of artificial intelligence (AI) chips has highlighted the critical contributions of various companies within the supply chain. Although NVIDIA Corporation is often recognized as the leader in AI advancements, the reality is far more intricate. A network of companies spans continents, from Asia to the United States, each playing vital roles in this complex ecosystem.

According to estimates from the United Nations, the AI market is projected to reach a staggering $4.8 trillion by 2033. This underscores the importance of identifying the organizations that are the backbone of the AI supply chain, which include wafer manufacturers from South Korea and Germany, software design providers in the U. S., and semiconductor producers in Taiwan.

Understanding the AI Chip Lifecycle: The Role of EDA Companies

Before a chip designer like NVIDIA can bring its creations to life, the foundational work is done by Electronic Design Automation (EDA) companies. While many believe the semiconductor industry predominantly exists in Asia, the reality is that many EDA firms are based in the United States. Therefore, the journey of creating an AI chip begins in America or Europe.

EDA companies are instrumental at the onset of chip design as well as during the verification of the product’s performance post-manufacturing, ensuring that AI chips adhere to high-performance standards. Prominent players in this arena include Cadence Design Systems, Synopsys, Ansys, and Siemens, which provide the tools essential for chip design and manufacturing.

By utilizing EDA simulation tools, chip designers can forecast the performance of their products and make adjustments before commencing the costly fabrication stage. Interestingly, a major share—approximately 70%—of the EDA market is dominated by a small trio of companies: Cadence, Synopsys, and Siemens.

Cadence Platforms — The Palladium Z3 Emulation Platform and Protium X3 Prototyping Platform. Image: Cadence Design Systems

Cadence, with revenues hitting $4.6 billion last fiscal year, supplies a broad spectrum of products focused on integrated circuit design as well as verification components. Synopsys, slightly smaller at $3.2 billion in revenue, is another key player. However, both companies rely heavily on a limited number of suppliers for essential hardware components, introducing vulnerabilities into the semiconductor supply chain.

EDA solutions such as Cadence’s Genus, Synopsys’ Fusion, and Siemens’ Oasys operate at the register-transfer-level (RTL) stage of semiconductor design, allowing designers to map data flow in the chip and simulate performance during the initial phase of design. This phase is crucial considering the complexity of today’s chip architectures, which may include billions of transistors, like Apple’s latest M4 chip featuring 28 billion transistors.

The intricacies of managing clock domain crossing (CDC) and reset domain crossing (RDC) errors are paramount during the design phase. To manage these, various verification tools enable engineers to validate and correct errors effectively. Notably, Cadence offers Conformal Litmus and Jasper CDC App, while Synopsys’s VC SpyGlass and Siemens’ Questa platforms support similar functionalities.

The RTL and CDC stages of AI chip design are crucial as designers strive to ensure that their netlist accurately reflects RTL specifications—a process that is often verified through layout versus schematic (LVS) checking using tools from leading EDA firms. Additionally, EDA companies supply emulation and prototyping systems that help designers confirm their products satisfy market needs.

Chip Manufacturing Simulation — A Synopsys image depicting the modeling of semiconductor manufacturing to identify potential errors. Image: Synopsys

Following the completion of the design processes, the next step involves packaging the chips to protect them and enable connectivity to printed circuit boards (PCBs).These packages can encompass several chiplets designed for specific functionalities, such as logic processing or memory storage, to enhance performance.

The ongoing demand for chips with billions of transistors necessitates that manufacturing processes acclimate to advanced specifications, employing cutting-edge techniques like sub-7-nanometer processes. These advanced technologies leverage extreme ultraviolet (EUV) lithography, reducing circuit sizes while accommodating larger transistor counts.

To meet these standards, EDA firms collaborate with organizations like TSMC to validate design tools that facilitate the efficient manufacture of advanced chips.

Translating Designs into Reality: The Crucial Role of TSMC

Once the design is finalized, the next and perhaps most perilous phase is execution, with Taiwan Semiconductor Manufacturing Company (TSMC) standing as a pivotal figure in AI chip production. TSMC is also the manufacturing force behind NVIDIA’s Blackwell AI GPUs, the most advanced chips available, which utilize a specialized variant of TSMC’s N4 node. Currently, most of the N4 production is centered in Taiwan, with an Arizona facility expected to ramp up production soon.

The production process begins with TSMC sourcing silicon wafers, relying primarily on 12-inch or 300mm wafers for N4 production from Fab 18 in Tainan, Taiwan. The supply chain for these wafers is extensive, with major suppliers located in South Korea, Germany, and Japan, including GlobalWafers, which operates a facility in Hsinchu, Taiwan.

Despite the diversity among wafer suppliers, reliance on ASML, the sole provider of advanced lithography equipment, poses challenges during chip manufacturing—a process that requires precision at every step. Lithography is fundamental to imprinting intricate designs on silicon wafers.

Semiconductor fabrication is complex and entails several stages, including the creation of photomasks crucial for transferring designs to wafers. TSMC independently manages this process, being the world’s leading photomask manufacturer, although it does rely on external suppliers for photoresists—key materials that can significantly impact manufacturing quality.

TSMC faced a notable setback in 2019 due to contaminated photoresist, underscoring the critical nature of this material in the production chain. Essential players in this supply chain include Shin-Etsu Chemical and Sumitomo Chemical alongside Japanese firms T. O.K and JSR, which supply essential photoresist components.

Tokyo Electron Coater — The Tokyo Electron Lithus Pro Z coater and developer, used in conjunction with ASML’s EUV machines. Image: Tokyo Electron

The importance of high-quality photoresist cannot be overstated, as any flaws during the lithography process can compromise chip integrity. The emergence of EUV technology has intensified the photoresist market due to its unique challenges, resulting in innovative alternatives such as Lam Research’s dry photoresist technology.

The lithographic processes also rely on protective pellicles to safeguard the photomask from contaminants during fabrication, and recent advancements in EUV have led to challenges in pellicle manufacturing capabilities. TSMC confirmed its development of in-house EUV pellicles to double its production capacity due to increased demand.

In subsequent stages of fabrication—etching, deposition, chemical mechanical polishing (CMP), metallization, and ion implantation—chemistry plays a crucial role. Each phase leverages a variety of gases and chemicals, forming the backbone of the AI chip manufacturing process.

For instance, plasma etching employs gases like argon and fluorine to achieve precise material removal. Chemical processes for deposition and CMP are equally varied, involving numerous suppliers of raw materials and specialty chemicals.

Plasma Etching Process — Image Credit: Samsung Semiconductor

Major chemical and gas suppliers such as DuPont, Fujifilm, and Merck contribute significantly to the diverse chemical landscape of AI chip fabrication. As demand grows, firms like Air Liquide and Nippon Sanso also play a vital role in providing essential industrial gases necessary for various fabrication processes.

This diversified chemical supply chain is more resilient compared to the other specialized areas of lithography and photomask industries. Even giants like DuPont and Merck provide critical substances across the full spectrum of AI chip production.

Final Stages: Packaging, Testing, and Beyond

Once the chips are fabricated, they undergo a packaging process to ensure functionality and compatibility with PCBs. This stage is vital as packaged chips, known as integrated circuits (ICs), must meet precise standards for performance and reliability.

Notably, packaging emerged as a bottleneck in NVIDIA’s AI chip supply chain, necessitating collaboration with TSMC for effective packaging solutions. The CoWoS (Chip-on-Wafer-on-Substrate) technique simplifies the packaging by integrating various components into a single package.

The primary materials used in packaging include insulating materials supplied by companies like Dow and DuPont, alongside underfill and redistribution layer (RDL) components provided by a variety of manufacturers.

CoWoS Package Structure — A schematic representation of CoWoS packaging by TSMC. Image: TSMC

After establishing the appropriate foundation, microballs and solder masks play critical roles in securing the chip on the substrate through flip-chip bonding techniques. This bonding process is essential to connect the chip and HBM (High-Bandwidth Memory) to the PCB efficiently.

Beyond the essentials, the substrate—often an ABF (Ajinomoto Build-up Film) substrate—forms the base and dictates thermal management for the chip. Key suppliers like Resonac and Panasonic contribute significantly to this aspect of the supply chain, ensuring advanced thermal properties for AI chips.

NVIDIA Chip Integration — The NVIDIA H100 AI chip package within a PCB configuration. Image: Patrick Kennedy/STH

Following the assembly of the package, the next step involves rigorous testing to check for defects and ensure performance standards. Companies like King Yuan ELECTRONICS and Advantest Corporation provide essential testing equipment for both wafer and system-level tests, with Chroma ATE Inc.believed to be NVIDIA’s primary SLT equipment supplier.

Once packaged and tested, these chips are integrated into server systems to facilitate AI computations in data centers. Hon Hai (Foxconn) and Wistron emerge as significant manufacturers for NVIDIA’s AI servers, culminating in a complex yet vital ecosystem that supports the AI chip supply chain.

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