Intel Director Reports on Future Importance of ASML’s High NA EUV Machines in Chip Manufacturing

Please note, this article is not intended as investment advice, and the author holds no stake in any of the stocks discussed herein.

Future Transistor Designs May Shift Semiconductor Manufacturing Paradigms

According to insights from an Intel director, advancements in future transistor designs could reduce the critical need for sophisticated lithographic equipment in high-end semiconductor production. Presently, ASML’s extreme ultraviolet (EUV) lithography systems are fundamental to contemporary chip manufacturing, allowing companies like TSMC to produce incredibly tiny circuits on silicon wafers. However, emerging designs—such as gate-all-around FET (GAAFET) and complementary FET (CFET)—may pivot the focus toward post-lithography processes, thereby diminishing the role of lithography in these advanced manufacturing techniques.

The Evolving Role of Etching in Chip Production

In a conversation shared on the investment research platform Tegus and disseminated via social media, the unnamed Intel director emphasized a notable shift in semiconductor fabrication processes. The director posits that as transistor designs evolve, the significance of advanced lithographic equipment may wane, giving more prominence to etching technologies. While EUV and high-NA EUV lithography machines are often spotlighted—especially against a backdrop of export restrictions—chip fabrication encompasses a range of intricate steps beyond just lithography.

Understanding the Chip Manufacturing Workflow

The lithography process serves as the initial phase where intricate designs are imprinted onto the silicon wafer. Following this, other essential processes, including deposition and etching, play critical roles. In deposition, various materials are layered onto the wafer, while etching is used to selectively remove excess material to delineate the patterns necessary for forming transistors and circuits.

Transistor Technologies: GAAFET and CFET

The Intel director highlighted how advanced transistor architectures like GAAFET and CFET could lessen reliance on traditional lithographic processes. EUV lithography has been pivotal in fabricating chips at the 7-nanometer scale and below, thanks to its precision in printing minuscule circuit designs. The evolution of transistor configurations—where current FinFET designs connect with the insulating base while new designs introduce wrapping of the gate around the transistor—illustrates this technological shift.

Transistor Evolution — A presentation from TSMC showcasing the evolution of transistors.

Implications for Manufacturing Strategies

With GAAFET and CFET designs enveloping the transistors, the removal of surplus material becomes increasingly vital. This “wrapping”approach necessitates lateral material removal, shifting priorities from merely enhancing lithographic feature sizes to refining etching techniques. The director notes that this transition implies a decreased reliance on high-NA EUV machines, suggesting that their importance may not match the previous generations of EUV scanners that were crucial for manufacturing 7-nanometer chips.

This shift could lead to a new era in semiconductor production, where vertical and lateral density can be achieved without a proportional increase in lithographic capabilities. The Intel executive concludes that this evolution in chip fabrication strategy may redefine industry benchmarks for performance and efficiency.

Director at Intel explains why ASML has been struggling due to GAA, and will struggle with the move to CFETs as well (via Tegus).The bright spot in terms of order flow can be high-NA adoption later this decade, or EUV multiple patterning, but clearly order flow will be highly… pic.twitter.com/ZoRvJJHC2n

— Tech Fund (@techfund1) June 16, 2025