Analysis of AMD EPYC Venice “Zen 6C” CPU Die Size: 32-Core “Zen 6C” CCDs Nearly Double the Size of Zen 5C CCDs with Dual 375mm²+ IO Dies

Recent analysis of AMD’s upcoming next-generation EPYC Venice CPU, built on the next-gen Zen 6C architecture, reveals significant enhancements in core counts and die size.

AMD Unveils EPYC Venice “Zen 6C”CPU: A Game Changer With Twice the Cores

During the CES 2026 event, AMD introduced its EPYC Venice CPU, powered by the revolutionary Zen 6 core architecture. This new chip showcases dramatic upgrades in core count and performance efficiency, marking it as the first data center CPU to utilize TSMC’s cutting-edge 2nm manufacturing technology.

The EPYC Venice “Zen 6″series now boasts eight robust Zen 6C chiplets and dual I/O dies, in addition to several auxiliary chiplets for management. AMD promises a staggering over 70% improvement in performance and efficiency, including more than a 30% increase in thread density. Available in configurations with a standard 192-core setup, each with 16 chiplets, features 12 Zen 6 cores and 768 MB of L3 cache.

A hand holding an unbranded computer processor against a dark background.

While not as gigantic as the MI455X, the EPYC Venice is still a formidable CPU, capable of featuring up to 256 cores. Central to each AMD EPYC Venice CPU is the new Zen 6C chiplet, now accommodating 32 cores—a remarkable doubling compared to its predecessor, the Zen 5C chiplet, which had 16 cores. Notably, each Zen 6C chiplet comes with 128 MB of L3 cache, culminating in a total of 1, 024 MB across the entire CPU.

A diagram showing the AMD Venice 256-core Zen 6 architecture using TSMC N2 and N6 processes. — Image Source: @highyieldYT

Regarding die size, the new Zen 6C chiplets of the EPYC Venice CPUs measure approximately 155mm², nearly double that of the Zen 5C chiplets, which span about 85mm². The new components are manufactured using TSMC’s N2P process, whereas the older Zen 5C chips utilized the N3E technology. This translates to an increase of 82.3% in die size from the previous generation, allowing for larger cache sizes and double the cores.

Venice IOD: ~375mm² N6 x 2Turin IOD: ~426mm² N6 x 1Zen6c CCD: 32 Cores = ~155mm² N2Zen5c CCD: 16 Cores = ~85mm² N3E https://t.co/n4GJGNWqlo

— Hassan Mujtaba (@hms1193) January 12, 2026

The AMD EPYC Venice series will integrate two large I/O dies, housing memory controllers, PCIe controllers, and various other intellectual properties, including AI-specific accelerators. Each I/O die, based on TSMC’s N6 technology, will measure around 375mm². In contrast, the previous generation EPYC Turin CPUs included a single I/O die measuring 426mm².

Key Comparisons Between AMD EPYC Venice and Previous Generations

Zen6c CCD: 32 Cores = ~155mm² N2
Zen5c CCD: 16 Cores = ~85mm² N3E

IOD Comparison:

Venice IOD: ~375mm² N6 x 2
Turin IOD: ~426mm² N6 x 1

CPU Performance Comparison:

EPYC 9006 “Venice”with Zen 6C: 256 Cores / 512 Threads / Up To 8 CCDs / 1024 MB L3
EPYC 9005 “Turin”with Zen 5C: 192 Cores / 384 Threads / Up To 12 CCDs / 384 MB L3
EPYC 9006 “Venice”with Zen 5: 96 Cores / 192 Threads / Up To 8 CCDs / 384 MB L3
EPYC 9005 “Turin”with Zen 5: 96 Cores / 192 Threads / Up To 16 CCDs / 384 MB L3

The dual I/O dies contribute an extensive total of 750mm² of die space dedicated solely to input/output functions, evident in AMD’s commitment to advancing the capabilities of its EPYC data center platforms. The upcoming AMD EPYC Venice CPUs will emerge as a powerhouse, ready to compete against Intel’s upcoming Diamond Rapids CPUs, built on the 18A node, which are also predicted to include 256 and 192-core options.

Overview of AMD EPYC CPU Families:

Family Name	AMD EPYC Summer	AMD EPYC Venice	AMD EPYC Turin-X	AMD EPYC Turin-Dense	AMD EPYC Turin	AMD EPYC Siena	AMD EPYC Bergamo	AMD EPYC Genoa-X	AMD EPYC Genoa	AMD EPYC Milan-X	AMD EPYC Milan	AMD EPYC Rome	AMD EPYC Naples
Family Branding	EPYC 9007	EPYC 9006	EPYC 9005	EPYC 9005	EPYC 9005	EPYC 8004	EPYC 9004	EPYC 9004	EPYC 9004	EPYC 7004	EPYC 7003	EPYC 7002	EPYC 7001
Family Launch	2027	2026	2025	2025	2024	2023	2023	2023	2022	2022	2021	2019	2017
CPU Architecture	It was 7	It was 6	It was 5	Zen 5C	It was 5	It was 4	It was 4C.	Zen 4 V-Cache	It was 4	It was 3	It was 3	It was 2	It was 1
Process Node	TBD	2nm TSMC	4nm TSMC	3nm TSMC	4nm TSMC	5nm TSMC	4nm TSMC	5nm TSMC	5nm TSMC	7nm TSMC	7nm TSMC	7nm TSMC	14nm GloFo
Platform Name	SP7	SP7	SP5	SP5	SP5	SP6	SP5	SP5	SP5	SP3	SP3	SP3	SP3
Socket	TBD	TBD	LGA 6096 (SP5)	LGA 6096 (SP5)	LGA 6096	LGA 4844	LGA 6096	LGA 6096	LGA 6096	LGA 4094	LGA 4094	LGA 4094	LGA 4094
Max Core Count	TBD	96	128	192	128	64	128	96	96	64	64	64	32
Max Thread Count	TBD	192	256	384	256	128	256	192	192	128	128	128	64
Max L3 Cache	TBD	TBD	1536 MB	384 MB	384 MB	256 MB	256 MB	1152 MB	384 MB	768 MB	256 MB	256 MB	64 MB
Chiplet Design	TBD	8 CCDs (1 CCX per CCD) + 2 IOD?	16 CCDs (1 CCX per CCD) + 1 IOD	12 CCDs (1 CCX per CCD) + 1 IOD	16 CCDs (1 CCX per CCD) + 1 IOD	8 CCDs (1 CCX per CCD) + 1 IOD	12 CCDs (1 CCX per CCD) + 1 IOD	12 CCDs (1 CCX per CCD) + 1 IOD	12 CCDs (1 CCX per CCD) + 1 IOD	8 CCDs (1 CCX per CCD) + 1 IOD	8 CCDs (1 CCX per CCD) + 1 IOD	8 CCDs (2 CCXs per CCD) + 1 IOD	4 CCDs (2 CCXs per CCD)
Memory Support	TBD	DDR5-12800	DDR5-6000?	DDR5-6400	DDR5-6400	DDR5-5200	DDR5-5600	DDR5-4800	DDR5-4800	DDR4-3200	DDR4-3200	DDR4-3200	DDR4-2666
Memory Channels	TBD	16-Channel (SP7)	12 Channel (SP5)	12 Channel	12 Channel	6-Channel	12 Channel	12 Channel	12 Channel	8 Channel	8 Channel	8 Channel	8 Channel
PCIe Gen Support	TBD	128-192 PCIe Gen 6	TBD	128 PCIe Gen 5	128 PCIe Gen 5	96 Gen 5	128 Gen 5	128 Gen 5	128 Gen 5	128 Gen 4	128 Gen 4	128 Gen 4	64 Gen 3
TDP (Max)	TBD	~600W	500W (cTDP 600W)	500W (cTDP 450-500W)	400W (cDP 320-400W)	70-225W	320W (cTDP 400W)	400W	400W	280W	280W	280W	200W