Synopsys Launches ‘Silicon Bring-Up’ of LPDDR6 IP on TSMC’s Advanced N2P Node, Achieving Exceptional Bandwidth of 86 GB/s

Synopsys has made a significant advancement in mobile memory technology by announcing the successful silicon bring-up of its LPDDR6 intellectual property (IP) based on TSMC’s cutting-edge N2P process node.

Impressive Bandwidth Achievements with N2P Technology

For those unfamiliar, silicon bring-up represents the initial power-up phase of a new chip, particularly relevant in the context of an IP block. This essential process involves a series of tests encompassing hardware validation, power sequencing, and other critical checks. Synopsys’s recent progress highlights its capability to develop a licensable LPDDR6 IP block that can reach extraordinary bandwidths of up to 86 GB/s, aligning closely with the specifications set by the JEDEC standards.

We’ve successfully achieved silicon bring up of our LPDDR6 IP on TSMC N2P, delivering up to 86GB/s bandwidth. Power next-gen mobile, AI, and edge systems with efficient LPDDR SDRAMs.

— Synopsys (@Synopsys) October 16, 2025

This development marks one of the first integrations of TSMC’s advanced N2P process with an LPDDR6 IP block. The architecture of this IP consists of two primary elements: the controller and the PHY interface. The controller is responsible for implementing the JEDEC protocol engine and managing timing controls and low-power states. Importantly, TSMC’s N2P process enhances the capabilities of the PHY, as it encompasses advanced analog and I/O circuits designed to optimize performance.

Notably, the LPDDR6 controller demands enhanced density and speed for efficient timing closure. The N2P technology excels in this area, boasting impressive power-performance-area (PPA) metrics. This not only reduces energy consumption per bit but also minimizes the physical footprint of the memory, facilitating its application in on-device AI and other power-efficient platforms.

Micron DDR5 MRDIMM with labels 256GB 8800MT/s 1U form factor and 128GB 8800MT/s displayed against a LPDDR6 backdrop.

Diving deeper into performance metrics, Synopsys reveals that the stack supports a remarkable bandwidth of 86 GB/s, aligning with JEDEC’s per-pin standard of approximately 10.667 Gb/s. The theoretical maximum speed could reach around 14.4 GB/s per pin, which equates to an impressive total bandwidth of 115 GB/s. This indicates that LPDDR6 represents a significant generational leap over LPDDR5, driven by the innovative enhancements from TSMC’s N2P technology. As we look ahead, LPDDR6 is poised to become a mainstream solution in the upcoming year, promising to redefine industry benchmarks for mobile memory.

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