Potential AMD RDNA 5 and UDNA GPU SKU Configurations Indicate 96, 40, 24, and 12 Compute Unit Dies

Recent insights from the leaker Kepler_L2 suggest new configurations for the AMD RDNA 5 / UDNA GPU family, indicating the presence of models with up to 96 Compute Units (CUs).

Diverse Die Configurations in the AMD RDNA 5 / UDNA Lineup: Up to 96 CUs

In July, speculative analysis by Kepler_L2 hinted at AMD’s forthcoming RDNA 5 / UDNA series. Renowned for providing accurate intel on AMD and Intel products as well as unannounced gaming consoles, Kepler_L2 has unveiled fresh details, including block diagrams of at least four distinct RDNA 5 / UDNA WeUs on the Anandtech Forums.

Top Variant Specifications

The highest-end AMD RDNA 5 / UDNA die is characterized by 8 Shader Arrays, each consisting of two Shader Engines, leading to a total of 16 Shader Engines. With each Shader Engine comprising six compute units, this configuration totals an impressive 96 CUs.

AMD RDNA 5 UDNA GPU Die Specs — Image Source: Kepler_L2 (via Anandtech Forums)

Each Shader Engine is paired with its dedicated Render Backed (RB) unit, all connected to a central SoC block featuring essential components, including the Graphics Command Processor, Graphics Engine, hardware scheduling (HWS) unit, and L2 cache. The architecture also accommodates 16 Unified Memory Controllers, each 32 bits wide, achieving a maximum bus size of 512 bits. If AMD maintains its current Infinity Cache (IFC) configuration, this top die could feature up to 128 MB of Infinity Cache.

Mid-Tier and Entry-Level Variants

Next in line is the 40 CU die, which hosts five CUs within each of its eight Shader Engines. This translates to a total of 40 CUs arranged in four Shader Arrays. Accompanied by six memory controllers, this variant offers a 192-bit bus interface and potentially supports up to 48 MB of Infinity Cache. The modular nature of the RDNA 5 SoCs, as highlighted during the Hot Chips event, suggests multiple configurations stemming from the upper-tier die.

Mid-tier RDNA 5 UDNA GPU Die Specs — Image Source: Kepler_L2 (via Anandtech Forums)

The entry-level RDNA 5 / UDNA dies feature configurations ranging from 24 to as few as 12 CUs. The 24 CU model includes four Shader Arrays with six compute units each, totaling 24 CUs, and features eight memory controllers. These could be configured for either 16-bit (maximum 128-bit bus) or 32-bit (maximum 256-bit bus) memory. It is considered less likely that AMD would offer a 256-bit setup for this tier compared to the 40 CU variant.

Entry-level RDNA 5 UDNA GPU Die Specs — Image Source: Kepler_L2 (via Anandtech Forums)

The most basic variant packs just two Shader Arrays, each featuring six compute units for a total of 12 CUs. This die comprises four memory controllers that may offer 32-bit (128-bit max) or 16-bit (64-bit max) configurations. Smaller dies in this category may include Infinity Cache specifications of up to 32 MB for the 24 CU model and 16 MB for the 12 CU variant.

Basic RDNA 5 UDNA GPU Die Specs — Image Source: Kepler_L2 (via Anandtech Forums)

Kepler_L2 also suggested the likelihood of enhanced local cache sizes per CU. The transition of the Instinct series from the CDNA 4 architecture, which featured 32KB L0 and 160 KB LDS cache, to 448 KB Shared L0/LDS cache in the upcoming CDNA 5 architecture for the MI400 series indicates a trend towards broader adaptations. While these developments primarily cater to datacenter applications, the potential unification of the Radeon and Instinct architectures under the UDNA banner beckons exciting possibilities for consumer-grade GPUs.

Forum post on the RDNA 5 UDNA specs — Image Source: Chiphell Forums

Furthermore, insights from Chiphell member ZhangZhonghao suggest the RDNA 4 lineup may also feature four configurations. These would include a flagship model, along with mid, low, and entry-tier WeUs. Although such claims warrant cautious optimism, AMD’s upcoming gaming GPU series is slated for mass production by Q2 2026, when further details will likely emerge.

Anticipated AMD RDNA 5 / UDNA GPU Configurations

GPU The	Ships 5X	Ships 5X	Ships 5X	Ships 5X
Positioning	Flagship-Tier	Mid-Tier	Low-Tier	Entry-Tier
Max Compute Units	96 CUs	40 CUs	24 CUs	12 CUs
Max Memory Bus	512-384 bit	384-192 bit	256-128 bit	128-64 bit
Max VRAM Capacity	24-32 GB	12-24 GB	8-16 GB	8-16 GB