Next-Gen HBM5 & HBM6 Memory Development in Progress with New Wide TC Bonders

The landscape of high-bandwidth memory (HBM) is on the brink of a significant transformation with the ongoing development of the next-generation HBM5 and HBM6 standards, facilitated by innovative TC Bonders.

Hanmi Semiconductor Unveils First Wide TC Bonders for Advanced HBM Technology

With NVIDIA and AMD gearing up to release their upcoming AI accelerators this year, which will be powered by HBM4 memory—such as the Vera Rubin and the Instinct MI450 series—research and development are already advancing towards the next iterations, HBM5 and HBM6.

A recent report by the Korean news outlet Heraldcorp indicates that the first Wide TC Bonder designed for the next-gen memory standards is set to debut at the 2026 Semiconductor Exhibition in Korea. This equipment will serve as an alternative to the Hybrid Bonder (HB) for the mass production of HBM memory.

NVIDIA Blackwell Chips — Image Credits: NVIDIA

The Wide TC Bonder stands out due to its ability to enhance production yields for various HBM standards, including HBM4, HBM4E, HBM5, and HBM6. Unlike its predecessor, the Hybrid Bonder, which encountered technical setbacks, the Wide TC Bonder employs advanced precision bonding technology to ensure superior quality and reliability during the production process.

One particularly interesting feature is its fluxless bonding capability that minimizes the oxide layer on chip surfaces, thus enhancing bond strength while simultaneously reducing the overall thickness of HBM.

HBM5: Targeting the NVIDIA Feynman Architecture with a Projected Launch in 2029

The HBM5 standard is anticipated to maintain an 8 Gbps data rate for its Non-e variant, while significantly increasing the number of IO lanes to 4096 bits. The bandwidth is projected to soar to 4 TB/s per stack, utilizing a 16-Hi stacking method. With the introduction of 40 Gb DRAM dies, HBM5 aims for a robust 80 GB capacity per stack and expects the power consumption per stack to reach 100W.

Key specifications for the HBM5 memory standard include:

Data Rate: 8 Gbps
Number of I/Os: 4096
Total Bandwidth: 4.0 TB/s
Number of Die Stacks: 16-Hi
Die Capacity: 40 Gb
Total HBM Capacity: 80 GB
Power per HBM: 100W
Packaging Method: Microbump (MR-MUF)
Cooling Solutions: Immersion Cooling, Thermal Via (TTV), Thermal Bonding
Dedicated Decoupling Capacitor Chip Die Stack
Custom HBM Base Die with 3D NMC-HBM & Stacked Cache
LPDDR+CXL in Base Die
Compatible with NVIDIA Feynman & Instinct MI500 Platforms

HBM6: A Leap Forward for Post-Feynman GPU Architecture

Setting the stage for even higher performance, HBM6 is expected to double the bandwidth to an impressive 8 TB/s while introducing 48 Gb capacities per DRAM die. This standard is also set to push the envelope on stacking technology by possibly exceeding the traditional 16-Hi configuration, reaching up to 20-Hi stacking. The anticipated memory capacity per stack could elevate to between 96-120 GB, with a stack power consumption of 120W. Both HBM5 and HBM6 are designed to incorporate immersion cooling solutions, with HBM6 exploring multi-tower HBM (Active/Hybrid) architectures, among other advanced features.

The core attributes of the HBM6 memory standard will likely include:

Data Rate: 16 Gbps
Number of I/Os: 4096
Total Bandwidth: 8.0 TB/s
Number of Die Stacks: 16/20-Hi
Die Capacity: 48 Gb
Total HBM Capacity: 96/120 GB
Power per HBM: 120W
Packaging Method: Bump-less Cu-Cu Direct Bonding
Cooling Solutions: Immersion Cooling
Custom Multi-Tower HBMs with Active/Hybrid Interposers
Integrated Network Switch + Bridge Die

As HBM4 is set to hit mass production soon, the momentum for HBM5 and HBM6 will ensure that these next-generation memory standards not only meet but exceed expectations with upgraded speeds and cutting-edge technological advancements over HBM4, heralding a new age of performance in memory technology.

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