Intel Nova Lake Compute Tile Die Sizes Unveiled: 8+16 Configuration at 110mm² & bLLC Variant Spanning 150mm²

Recent revelations about Intel’s Nova Lake compute tiles have unveiled die sizes, with the base die being marginally smaller than the compute tile of Arrow Lake.

Intel’s Nova Lake bLLC Compute Tile: Size Insights and Dual Variants

As details about Intel’s Nova Lake CPUs continue to emerge, the latest information comes from HXL, highlighting the die sizes of the compute tiles configured in an 8+16 setup.

Intel’s design for the Nova Lake CPUs, applicable for both desktops and laptops, will utilize this 8+16 architecture, which will then be adapted into various WeUs. Additionally, an entry-level 4+8 WeU is expected. The manufacture of all compute tiles is taking place on TSMC’s advanced N2 process technology, in contrast to the 18A fabrication planned for Panther Lake chips, although there is a possibility we might see an 18A compute tile as per the ongoing roadmap discussions.

The core structure of Intel’s Nova Lake CPUs includes 8 P-Cores based on the Coyote Cove technology and 16 E-Cores grounded in the Arctic Wolf design. Furthermore, these processors will integrate 4 low-power E-Cores on a dedicated “low-power island, ”which cannot be overclocked but can be utilized either in isolation (with both P/E cores disabled) or in conjunction with E-Core clusters. Furthermore, the P-Cores are organized in pairs within clusters, providing 4 MB of L2 cache for each pair.

NVL 8+16 The TSMC N2 ~110+mm2 NVL 8+16 bLLC The TSMC N2 ~150+mm2 https://t.co/beHNikpl1O

— HXL (@9550pro) February 11, 2026

The standard Nova Lake die, equipped with 8 P-Cores, 16 E-Cores, and 4 LPE cores, is estimated to be approximately 110 mm², slightly smaller than Arrow Lake’s compute tile, which measures 117.2 mm². Additionally, the bLLC (big cache) variants will introduce 144 MB of cache per compute tile, with the bLLC 8+16 die increasing the size to approximately 150 mm², displaying a 36.6% increase and being 28% larger than Arrow Lake’s compute tile.

Early information on the dual compute tile variants indicates that the standard “Non-bLLC”versions will have a total size of about 220 mm², while the bLLC variants, which can support up to 52 cores and 288 MB of L3 cache (320 MB when considering L2 + L3), are projected to occupy around 300 mm². This is a significant allocation of die area; however, it’s worth noting that all these configurations will fit within the same package and socket, eliminating the need for a separate platform for dual or bLLC configurations.

When positioned against AMD’s forthcoming Zen 6 and current Zen 5 architectures, the differences in die sizes are notable. AMD’s Zen 5 currently features 8 cores per CCD, with each die measuring 71 mm². Zen 6 is anticipated to offer 12 cores per CCD, with an estimated die size of 76 mm².

In a comparative analysis, Intel’s standard 8+16 compute tile is about 55% larger than the Zen 5 CCDs while offering three times the core count. Compared to the Zen 6, it is 44% larger with double the core count. Furthermore, while the bLLC die will be larger and accommodate more cores, AMD employs X3D stacking technology, enabling additional cache to be integrated directly on or beneath the CCD without expanding die dimensions, which is a feature not being utilized in Nova Lake.

Here’s a summary of relevant die sizes:

Intel Nova Lake 8+16 (Standard Compute Tile): ~110mm²
Intel Nova Lake 8+16+144 MB (bLLC Compute Tile): ~150mm²
Intel Nova Lake 16+32 (Dual Compute Tile): ~220mm²
Intel Nova Lake 16+32+288 MB (bLLC Dual Compute Tile): ~300mm²
AMD Zen 5 8 Core CCD + 32 MB/64 MB X3D: ~71mm²
AMD Zen 6 12 Core CCD + 48 MB/TBD MB X3L3: ~76mm²

This concludes the latest insights on Intel’s Nova Lake-S desktop CPUs, providing a clearer perspective on the anticipated specifications and competitive landscape. Intel’s Nova Lake-S CPUs, paired with the upcoming 900-series motherboards, are set to launch later this year. They will face off against AMD’s Zen 6-based Ryzen products, which bring in fresh architectural and platform innovations, paving the way for an intriguing competition in the latter half of 2026.

Comparative Overview: Nova Lake-S vs Arrow Lake-S

Feature	Nova Lake-S	Arrow Lake-S
Max Core Count	52	24
Max Thread Count	52	24
Max P-Cores	16	8
Max E-Cores	32	16
Max LP-E Cores	4	0
Max Cache (L2+L3)	160-320 MB	76 MB
Max bLLC Cache	144-288 MB	N/A
DDR5 (1DPC 1R)	8000 MT/s	7200-6400 MT/s
Max PCIe 5.0 Lanes	36	24
Max PCIe 4.0 Lanes	16	4
Socket Support	LGA 1954	LGA 1851
Max TDP (PL1)	125-175W	125W
Max Power	~700W (Dual)~350W (Single)	~400W
Expected Launch	2H 2026	1H 2026