
Intel has unveiled its innovative 18A process node, set to succeed the Intel 3 node, with enhancements in clock speeds and voltage scalability that promise to elevate performance across various applications.
Introducing the Intel 18A Process Node: A Leap Forward
During the 2025 Symposium on VLSI Technology and Circuits, Intel showcased its cutting-edge 18A process node. This new technology will power future product lines, such as the “Panther Lake”CPUs aimed at consumer markets and the Clearwater Forest E-Core-only Xeon processors targeting servers.
Advanced CMOS Technology
“Intel 18A Platform Technology Featuring RibbonFET (GAA) and Power Via for Advanced High-Performance Computing” – Intel (Paper T1-1).The groundbreaking 18A technology utilizes RibbonFET and Power Via, delivering over 30% density scaling and a comprehensive performance boost compared to Intel 3. It includes high-performance (HP) and high-density (HD) libraries designed for optimal usability and innovation in chip architecture.
The standout features of Intel’s 18A node center around the RibbonFET technology and PowerVia. These advancements pave the way for enhanced efficiency and a transition to next-generation processing technologies.

Intel’s shift to 18A RibbonFET technology marks a substantial advancement over FinFET processes. It improves gate electrostatics, maximizes effective gate width per footprint, decreases parasitic capacitance, and enhances design flexibility.

The design improvements of RibbonFET over FinFET encompass various aspects, including:
- Multiple ribbon widths for 180H and 160H libraries.
- Optimal logic power/leakage trade-offs achieved through design technology co-optimization (DTCO).
- Specialized ribbon widths for SRAM tailored to enhance bitcell performance.

Power delivery also sees significant enhancements through Intel’s 18A PowerVia technology, utilizing backside power signal wires instead of front-side connections. This innovative approach allows for:
- Enhanced logic density.
- Superior standard cell utilization.
- Reduced signal resistance-capacitance (RC).
- Minimized voltage droop.
- Increased design flexibility.
Intel 18A Specifications
HP/DR Library Height (nm) | 180/160 |
---|---|
Contacted Poly Pitch (nm) | 50 |
M0 Pitch (nm) | 32 |
HCC/HDC SRAM area | 0.023/0.021 µm² |
# of Frontside Metal Layers | 10ML Low cost, 10ML high density, and 14-16ML high performance |
# of Backside Metal Layers | 3ML+3ML |

With these technological advancements, Intel’s 18A process node achieves over a 15% performance gain under iso-power conditions compared to Intel 3.

At a voltage of 1.1V, the 18A node delivers approximately 25% higher frequency performance. Additionally, it supports low-voltage operations below 0.65V, achieving power savings of up to 38% at equivalent clock speeds. Key contributors to these performance enhancements include:
- RibbonFET transistors.
- Backside power delivery advantages.
- Improved interconnects on the front side.
- Process and design co-optimization.





For density scaling, Intel’s 18A node demonstrates up to a 39% improvement in density compared to Intel 3, with the backside power technology achieving an 8-10% increase in cell utilization while significantly reducing worst-case IR droop by a factor of 10. Additionally, it offers an HP Library Height of 180nm compared to 240nm in Intel 3, along with an HD Library Height of 160nm versus 210nm in Intel 3, and an M0/M2 pitch of 32/32 versus 30/42 in Intel 3.


In terms of SRAM scaling, the 18A node achieves a density improvement of 30% for HCC SCRAM compared to Intel 3, offering HCC at 0.0230 µm² and HDC at 0.0210 µm². Furthermore, Intel has plans for iterative improvements on the 18A node with additional variants, such as 18A-P and 18A-PT, set for introduction between 2026 and 2028, encouraging customers to capitalize on these advancements in their chip production.
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