
At the Hot Chips 2025 conference, IBM introduced its advanced Power11 CPU, featuring cutting-edge 2.5D Stacking technology, increased clock speeds, and memory systems enhanced with AI acceleration.
Enhancements in AI Acceleration and Processing Power with IBM’s Power11 CPU
The launch of the Power11 CPU architecture marks a significant step forward from its predecessor, Power10, which employed Samsung’s early 7nm process technology. In a notable shift, IBM opted for an optimized enhanced 7nm node for Power11. This change caters to client demands for increased speed over density, avoiding a premature transition to the 5nm process.

IBM has deepened its collaboration with Samsung to leverage not only process technology but also innovative packaging techniques such as iCube SI Interposer technology. This allows for 2.5D stacking, which enhances the system architecture by optimizing power delivery and improving overall performance.

A key objective during the development of Power11 was increased processing speeds and enhanced threading capabilities. Retaining a similar architecture to Power10, Power11 supports 16 cores per chip with an impressive 160 MB cache. The dual-socket CPU designs now support configurations ranging from 40 to 60 processor cores, with clock speeds elevated from 4.0 GHz to 4.3 GHz.

Incorporating in-core MMA (Multiply-Matrix-Accumulator) functionality on each Power11 CPU core, the architecture is complemented by external ASICs or GPUs that support Spyre Accelerators. These advancements lead to significant performance boosts across various system configurations, with improvements of up to 50% in smaller systems, about 30% in mid-tier solutions, and an average increase of 14% in top-tier systems.


Power11 also incorporates Quantum Safe Security features, which are essential as we advance towards a future influenced by quantum computing. This functionality is particularly emphasized in IBM’s Z mainframe systems, ensuring robust security measures.

On the memory front, IBM has made significant strides as well. The Power11 architecture supports up to 32 DDR5 ports in a single socket, quadrupling the capacity and bandwidth compared to previous generations that used 8 DDR5 ports. This new design uses a unique DIMM form factor that fits under a copper heatsink, with indications of future support for DDR6 in subsequent Power systems.

IBM’s improved memory system is designed to be hardware agnostic, providing compatibility with both DDR4 and DDR5 interfaces. Future upgrades may also include support for DDR5 and DDR6.
Key Advancements in OMI Memory Architecture
- Increased Bandwidth: Up to 1200 GB/s DRAM per socket, a threefold improvement.
- Enhanced Capacity: Up to 8 TB DRAM per socket, doubling previous capacities.
- Improved Coherence Flow: Achieving 1000 GB/s across the system, an increase of 1.3 times.


Looking to the future, IBM has hinted at the development of its next-generation Power CPU, which will feature a triplet architecture. Interestingly, some thermal innovations from this upcoming design have already been integrated into the Power11 architecture.
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