
During Hot Chips 2025, Google showcased its revolutionary next-generation TPU platform, known as Ironwood, emphasizing its extensive scalability at the rack level.
Exploring Google’s Ironwood: A Leap Forward in TPU Technology
The Ironwood platform, which represents the 7th Generation of TPUs, was initially unveiled in April 2023. Google announced that this architecture promises an extraordinary 24-fold increase in performance compared to the current leading supercomputers. In its Hot Chips 2025 presentation, Google provided an overview of its TPU evolution and advancements over the years.

In 2022, Google rolled out TPU v4, which integrated 4096 chips in a single pod, accompanied by 32 GB of 1.2 TB/s high-bandwidth memory (HBM) and offering 275 TFLOPs of computational power per chip. The following year, the TPU v5p was introduced, featuring 8960 chips, 95 GB of 2.8 TB/s HBM memory, and an impressive 459 TFLOPs per chip. This year, the Ironwood TPU Superpod is set to elevate these specifications further, providing 9216 chips per pod, equipped with 192 GB of 7.4 TB/s HBM memory and a staggering 4614 TFLOPs of peak performance per chip, marking a 16-fold improvement over the TPU v4.

Google delved deeper into the architecture of the Ironwood Superpod and the Max-scale cluster. At the core of this architecture lies the Ironwood system-on-chip (SoC), with four chips integrated into each Ironwood PCBA motherboard, which collectively fit into an Ironwood TPU rack. Each rack holds 16 Ironwood PCBAs, equating to a formidable 64-chip configuration.

The networking solution for interconnectivity utilizes Google’s InterChip Interconnect (ICI) technology, designed for scale-up networking. This setup can link up to 43 clusters (with one block comprising 64 chips each) across Superpods, facilitated by a substantial 1.8 Petabytes network capacity. Internal data exchange employs various network interface cards (NICs).
Google’s superpod consists of multiple racks, specifically the Ironwood Superpod featuring 144 racks. Additionally, the architecture includes an optical switch chassis to enhance scale-up connectivity across blocks, complemented by a coolant distribution unit (CBU) rack.

The design of the racks employs a 3D Torus layout, maintained consistently across the last three generations of TPUs. Each structural component comprises a 4x4x4 3D network, totaling 64 chips or nodes packaged within a single rack.

Google’s interconnectivity strategy employs a hybrid model that combines printed circuit board (PCB) sheets, copper passive links, and fiber optic connections to ensure flexibility in system configuration.





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The upper section of each rack is equipped with a drip pan to monitor for potential liquid leaks from the manifold. Below this is the power delivery system, which features two power domains capable of converting 416 volt AC into DC through rectification. Ironwood’s design implements a liquid cooling system, enabling a single rack to support over 100 kW of power under full load. This concludes the insights shared regarding the Ironwood TPU.
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