Detailed Overview of AMD SP7 & SP8 Platforms for Next-Gen EPYC “Venice” & “Verano” CPUs: 12800 MT/s 16-Channel Memory and 128 PCIe 6.0 Lanes

AMD has recently unveiled the SP7 and SP8 platforms, designed to support the forthcoming EPYC “Venice”and “Verano”CPUs, featuring advanced DDR5 memory and PCIe 6.0 support.

AMD Elevates Server I/O with SP7 & SP8 Platforms for EPYC “Venice”and “Verano”CPUs

In a press release earlier today, AMD shared details about the highly anticipated EPYC Venice and Verano CPUs. The Venice variant is expected to offer an impressive 256 cores utilizing the Zen 6C architecture, with a projected launch in 2026. The Verano, potentially an enhanced version of Zen 6 or an entirely new Zen 7 architecture, is set to be released in 2027. Although specific technical details remain limited from AMD, leaks have begun to shed light on the capabilities of these innovative platforms.

Exploring the SP7 Platform

The SP7 platform demonstrates AMD’s commitment to high performance, providing support for up to 16-channel DDR5 memory, achieving speeds up to 8000 MT/s with ECC modules and 12, 800 MT/s for MRDIMMs in a 1DPC configuration. Further enhancing its capabilities, the platform will accommodate various memory interleave configurations (1, 4, 8, and 16 channels) and broaden its compatibility to include RDIMM, 3DS RDIMM, MRDIMM, and Tall DIMM DRAM solutions.

AMD SP8 Server Platform — Image Source: Baidu Forums

From an I/O standpoint, the SP7 will maintain dual-socket (2P) support, offering up to 128 PCIe Gen 6.0 lanes, each capable of delivering a bandwidth of 64 Gbps. Additionally, the platform includes up to 16 “Bonus”PCIe Gen 4 lanes. For single-socket (1P) configurations, it will provide up to 96 lanes of PCIe Gen 6.0 along with 8 additional Gen 4 lanes, supporting Smart Data Cache Injection (SDCI).

AMD SP7 Server Platform — Image Source: Baidu Forums

SP8 Platform Overview

Positioned as an entry-level solution, the SP8 platform is also built to support the next generation of EPYC processors. While it mirrors SP7’s memory compatibilities, it operates in an 8-channel configuration. Notably, the SP8 boasts a higher count of PCIe Gen 6.0 lanes than its counterpart, with up to 192 lanes on dual-socket setups and 128 lanes on single-socket configurations.

AMD EPYC Venice Zen 6C CPU — Image Source: Baidu Forums

CPU Configurations and Expectations

The upcoming Zen 6C and Zen 6 Dense CPUs will feature up to 32 cores per chiplet (CCD), amounting to a total of 8 CCDs. This configuration allows AMD to achieve the anticipated 256-core total highlighted during the announcement. Each chiplet includes 128 MB of L3 cache, culminating in an impressive 1 GB of cache across the entire CPU. Notably, each chip consists of two I/O dies that furnish PCIe Gen 6.0 and CXL 3.1 functionalities, along with support for DDR5-8000 memory. Interestingly, one diagram specifies the maximum MRDIMM speed at 10, 400 MT/s, contrasting the earlier stated 12, 800 MT/s.

AMD EPYC Venice Zen 6 CPU — Image Source: Baidu Forums

Standard EPYC “Venice”offerings, based on the traditional Zen 6 architecture, will consist of 12 cores per CCD, with a total of 8 CCDs featured in a similar dual I/O die setup. This results in a total of 96 cores and 192 threads, matching the core count of the existing Turin series.

EPYC 9006 “Venice”with Zen 6C: 256 Cores / 512 Threads / Up To 8 CCDs
EPYC 9005 “Turin”with Zen 5C: 192 Cores / 384 Threads / Up To 12 CCDs
EPYC 9006 “Venice”with Zen 5: 96 Cores / 192 Threads / Up To 8 CCDs
EPYC 9005 “Turin”with Zen 5: 96 Cores / 192 Threads / Up To 16 CCDs

This information highlights AMD’s continued ambition to enhance core counts, computational power, and I/O features, retaining its status as a leader in the server market. With the Venice CPUs launching in 2026 and followed by the Verano series in 2027, the data center landscape is poised for exciting advancements.

AMD EPYC CPU Family Overview

Family Name	AMD EPYC Summer	AMD EPYC Venice	AMD EPYC Turin-X	AMD EPYC Turin-Dense	AMD EPYC Turin	AMD EPYC Siena	AMD EPYC Bergamo	AMD EPYC Genoa-X	AMD EPYC Genoa	AMD EPYC Milan-X	AMD EPYC Milan	AMD EPYC Rome	AMD EPYC Naples
Family Branding	EPYC 9007	EPYC 9006	EPYC 9005	EPYC 9005	EPYC 9005	EPYC 8004	EPYC 9004	EPYC 9004	EPYC 9004	EPYC 7004	EPYC 7003	EPYC 7002	EPYC 7001
Family Launch	2027	2026	2025	2025	2024	2023	2023	2023	2022	2022	2021	2019	2017
CPU Architecture	It was 7	It was 6	It was 5	Zen 5C	It was 5	It was 4	It was 4C.	Zen 4 V-Cache	It was 4	It was 3	It was 3	It was 2	It was 1
Process Node	TBD	2nm TSMC	4nm TSMC	3nm TSMC	4nm TSMC	5nm TSMC	4nm TSMC	5nm TSMC	5nm TSMC	7nm TSMC	7nm TSMC	7nm TSMC	14nm GloFo
Platform Name	SP7	SP7	SP5	SP5	SP5	SP6	SP5	SP5	SP5	SP3	SP3	SP3	SP3
Socket	TBD	TBD	LGA 6096 (SP5)	LGA 6096 (SP5)	LGA 6096	LGA 4844	LGA 6096	LGA 6096	LGA 6096	LGA 4094	LGA 4094	LGA 4094	LGA 4094
Max Core Count	TBD	96	128	192	128	64	128	96	96	64	64	64	32
Max Thread Count	TBD	192	256	384	256	128	256	192	192	128	128	128	64
Max L3 Cache	TBD	TBD	1536 MB	384 MB	384 MB	256 MB	256 MB	1152 MB	384 MB	768 MB	256 MB	256 MB	64 MB
Chiplet Design	TBD	8 CCDs (1 CCX per CCD) + 2 IOD?	16 CCDs (1 CCX per CCD) + 1 IOD	12 CCDs (1 CCX per CCD) + 1 IOD	16 CCDs (1 CCX per CCD) + 1 IOD	8 CCDs (1 CCX per CCD) + 1 IOD	12 CCDs (1 CCX per CCD) + 1 IOD	12 CCDs (1 CCX per CCD) + 1 IOD	12 CCDs (1 CCX per CCD) + 1 IOD	8 CCDs (1 CCX per CCD) + 1 IOD	8 CCDs (1 CCX per CCD) + 1 IOD	8 CCDs (2 CCXs per CCD) + 1 IOD	4 CCDs (2 CCXs per CCD)
Memory Support	TBD	DDR5-12800	DDR5-6000?	DDR5-6400	DDR5-6400	DDR5-5200	DDR5-5600	DDR5-4800	DDR5-4800	DDR4-3200	DDR4-3200	DDR4-3200	DDR4-2666
Memory Channels	TBD	16-Channel (SP7)	12 Channel (SP5)	12 Channel	12 Channel	6-Channel	12 Channel	12 Channel	12 Channel	8 Channel	8 Channel	8 Channel	8 Channel
PCIe Gen Support	TBD	128-192 PCIe Gen 6	TBD	128 PCIe Gen 5	128 PCIe Gen 5	96 Gen 5	128 Gen 5	128 Gen 5	128 Gen 5	128 Gen 4	128 Gen 4	128 Gen 4	64 Gen 3
TDP (Max)	TBD	~600W	500W (cTDP 600W)	500W (cTDP 450-500W)	400W (cDP 320-400W)	70-225W	320W (cTDP 400W)	400W	400W	280W	280W	280W	200W