TSMC Plans A13 “1.3nm” & A12 “1.2nm” Process Nodes for 2029, Avoids ASML’s Most Expensive EUV Equipment for the Time Being

At the recent North American Technology Symposium held in 2026, TSMC unveiled its ambitious technology roadmap, projecting advancements through 2029 with cutting-edge processes including the upcoming A13 and A12 nodes.

TSMC’s Strategic Focus: Cost Constraints and Future Innovations

During the symposium, TSMC outlined significant updates within its roadmap that emphasize process optimization and the integration of new technologies. Their strategy seems particularly focused on refining area sizes and enhancing efficiency across various applications.

A slide titled 'TSMC Advanced Technology Roadmap' showing production years from 2021 to 2029 with major nodes like N5P, N4, N3E, and A14, alongside mainstream nodes such as N6, N4C, and N3C.

The roadmap showcases TSMC’s dedication to technological progression, starting with its N2 process technology, which is set for mass production in the current year. Subsequent advancements include the upcoming N2P/N3A slated for 2026, followed by N2X/A16 in 2027, A14/N2U in 2028, and finally, the A13/A12 processes in 2029. In tandem with these high-end offerings, TSMC plans to release mainstream-optimized technologies like N3C in 2026 and N2U targeting both premium and mainstream markets.

A Deep Dive into the TSMC A13 (1.3nm) Process Node

TSMC has revealed that its A13 (1.3nm) process technology is an evolution of the A14 node, featuring a significant 6% reduction in area. This compact node is tailored for high-performance computing (HPC), artificial intelligence (AI), and mobile applications, ensuring backward compatibility with A14. Production is projected to commence in 2029, following the anticipated launch of A14 (1.4nm).

A TSMC presentation slide titled 'A13 Extends Technology Leadership' shows a 97% optical shrink with 6% area saving, targeting production in 2029.

Exploring the TSMC A12 (1.2nm) Process Node

Scheduled for production by 2029, the A12 (1.2nm) node further enhances the A14 architecture, utilizing TSMC’s Super Power Rail technology for more efficient backside power delivery. This innovation is aimed at achieving superior performance benchmarks in the semiconductor landscape.

Introduction to the TSMC N2U (2nm) Process Node

The N2 (2nm) platform will see the debut of the N2U node, promising speed enhancements between 2-4% or an 8-10% power reduction at equivalent performance levels. It will achieve a 1.02-1.03x increase in logic density compared to N2P, making it an attractive option for AI, HPC, and mobile applications. With increased maturity built on the N2 foundation, this new node is expected to commence production in 2028.

Beyond these advancements, TSMC is also innovating in packaging solutions, including 3D Silicon Stacking and 3D Fabric technologies.

A slide from TSMC titled 'N2U Maximizes Technology Platform Values' highlights enhancements in PPA and lists production planned for 2028, comparing 'N2U PPA (vs. N2P)' with speed and power metrics.

TSMC’s renowned CoWoS (Chip-on-Wafer-on-Silicon) packaging technology is set to enable the production of larger products, reaching up to 5.5-reticle sizes. The company has ambitious plans for a 14-reticle size CoWoS die solution, capable of integrating 10 compute dies and 20 HBM stacks, projected for production in 2028. By 2029, further advancements will lead to the introduction of a 40-reticle size SoW-X technology.

In a relatable context, OpenAI has recently unveiled a patent utilizing embedded interconnect bridges to develop larger dies, aiming to transcend the boundaries set by current CoWoS technologies. This innovation opens up exciting possibilities for packaging advancements in the semiconductor industry.

TSMC continues to expand its TSMC-SoIC® 3D chip stacking technology on its cutting-edge platforms, with A14-to-A14 SoIC targeting production in 2029, boasting 1.8X higher die-to-die I/O density compared to N2-on-N2 SoIC, thereby enhancing bandwidth in data transfer.
The Compact Universal Photonic Engine (TSMC-COUPE™) will reach a pivotal milestone, with true co-packaged optics solutions leveraging COUPE on substrate set for production in 2026. This integration directly inside packages offers a remarkable 2X power efficiency and a 10X reduction in latency compared to conventional pluggable optics.

Notably, TSMC has chosen to forgo the use of ASML’s advanced EUV machines through 2029. This decision is not due to a lack of necessity for these machines; indeed, they are essential for the next generation of technologies. However, the financial burden of acquiring these sophisticated lithography tools is currently deemed too high, especially as companies redirect investments toward establishing new fabs driven by the surging demand for AI technology. Thus, TSMC will rely on existing EUV machines to facilitate the production of efficient and optimized upcoming nodes like A13 and A12.

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