AMD is gearing up to unveil its next-generation Zen 6 CPUs, which will be manufactured using TSMC’s advanced N2 process node. Notably, the new Zen 6 CCD promises a significant leap in core density, boasting a 50% increase in the number of cores compared to its predecessors.
AMD’s 2nm Zen 6 CCD Boosts Core Density: 50% More Cores with TSMC’s N2 Technology
The incoming Zen 6 architecture is set to introduce robust improvements, and current insights reveal key specifications about the CCD (Chiplet Die).The advancements come from a trusted source, HXL (@9550pro), who revealed comparative die sizes for AMD’s CCD generations.
Zen2 CCD: 2*4 Core 2*16 MB L3 TSMC N7 ~77 mm2Zen3 CCD: 8 Core 32MB L3 TSMC N7 ~83 mm2Zen4 CCD: 8 Core 32MB L3 TSMC N5 ~72 mm2Zen5 CCD: 8 Core 32MB L3 TSMC N4 ~71 mm2Zen6 CCD: 12 Core 48MB L3 TSMC N2 ~76 mm2
— HXL (@9550pro) January 30, 2026
AMD has confirmed that its EPYC Venice CPUs will be the first to utilize the Zen 6 CCDs, manufactured using TSMC’s cutting-edge N2 NanoSheet technology. Recent reports suggest that AMD is likely to implement TSMC’s N2P process across the entire Zen 6 lineup, while some entry-level models may still depend on the N3P process.
Current CCD Die Sizes: A Quick Comparison
- Zen2 CCD: 2*4 Core, 2*16 MB L3, TSMC N7, ~77 mm²
- Zen3 CCD: 8 Core, 32 MB L3, TSMC N7, ~83 mm²
- Zen4 CCD: 8 Core, 32 MB L3, TSMC N5, ~72 mm²
- Zen5 CCD: 8 Core, 32 MB L3, TSMC N4, ~71 mm²
- Zen6 CCD: 12 Core, 48 MB L3, TSMC N2, ~76 mm²
Interestingly, the Zen 6 CCD will have a die size of 76 mm², comparable to previous generations like the Zen 5 and Zen 4, which measured 71 mm² and 72 mm², respectively. This results in a modest increase of only 5-7% in die size, yet a notable enhancement in core and cache capacity. Each Zen 6 CCD will feature 12 cores, an upgrade from the previous 8 cores, and it will be accompanied by 48 MB of L3 cache compared to 32 MB in the last generation, achieving a substantial 50% boost in both core and cache counts.
Expected Features of AMD Ryzen “Zen 6″Desktop CPUs
- Potential for Double-Digit IPC Improvements
- Increased Core & Thread Counts (Possibly Up To 24/48)
- Enhanced Clock Speeds on Advanced Process Node
- Expanded Cache (Possibly Up To 48 MB Per CCD)
- Support for Up To 2x CCDs & 1x IOD
- Improved DDR5 Memory Speed Support
- Maintain Dual-Channel Configuration with Dual IMC Design
- Similar Thermal Design Power (TDP) Levels
The increase in core and cache density illustrates the remarkable capabilities of TSMC’s new N2 node, which AMD is poised to leverage for significant performance enhancements. Additionally, the Zen 6 CCD illustrates an ambitious leap with a die size around 156 mm² while accommodating an extraordinary 32 cores and 128 MB of L3 cache per CCD—translating to roughly double the core count and a 2.66-fold increase in cache capacity compared to the prior generation.
As AMD continues to enhance its Zen 6 architecture, the improvements are anticipated to play a pivotal role in elevating performance across servers, desktops, and mobile platforms. We can also expect notable gains in IPC, increased clock speeds, and further enhancements, particularly in the upcoming X3D 3D V-Cache technology, likely to debut in the new chips. The first Zen 6 CPUs, including the EPYC Venice and the next-gen Ryzen family, are slated for release in the latter half of this year. Stay tuned for more updates.
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