Recent developments regarding AMD’s upcoming SP8 and SP7 sockets have unveiled significant advancements designed for the new Zen 6-powered EPYC Venice and Verano CPUs. These innovations reflect AMD’s commitment to enhancing compute density and overall performance.
AMD Unveils SP8 & SP7 Sockets for EPYC Venice & Verano CPUs
Last year marked the announcement of AMD’s EPYC Venice and EPYC Verano CPUs. The Venice line is poised to introduce up to 256 cores utilizing the Zen 6 architecture, with an anticipated launch in 2026. Meanwhile, the Verano series, expected in 2027, will provide a more affordable alternative built on the same Zen 6 platform.
HELM Technology, a leading Taiwanese component manufacturer, has outlined the technical details surrounding the new sockets. The SP7 socket will measure 123.6 x 100.6 mm, representing a 12% increase in size compared to the existing SP5 sockets that support the EPYC Genoa and Turin CPUs. This revamped design incorporates a Socket Retention Mechanism (SRM) and consists of four key layers: the SRM on top, a middle carrier board, housing on the motherboard, and a backplate, all of which are engineered for optimal performance.
The second socket, SP8, designed specifically for the EPYC Verano CPUs, features a footprint of 123.9 x 80.9 mm, making it slightly larger by 7% compared to its predecessor, the SP6. A notable upgrade for SP8 is the implementation of the SRM load mechanism, diverging from the Socket Actuation Mechanism (SAM) used in SP6.
Key Features of the AMD SP7 Platform
The SP7 platform is set to maximize performance capabilities, supporting up to 16-channel DDR5 DRAM with impressive speeds of up to 8000 MT/s ECC and 12, 800 MT/s MRDIMMs in 1DPC configurations. This platform will cater to memory types including RDIMM, 3DS RDIMM, MRDIMM, and Tall DIMM solutions while maintaining support for multiple memory interleaves.
When examining the I/O capabilities, the AMD SP7 platform will support dual sockets, allowing two next-gen sockets per motherboard, and offer an expansive bandwidth with up to 128 PCIe Gen 6.0 lanes, each capable of delivering 64 Gbps. Additionally, it provides up to 16 “Bonus”PCIe Gen 4 lanes for enhanced functionality.
In summary, the AMD SP7 platform features:
- Up to 16-Channel DDR5 Support
- DDR5 ECC Memory Speeds Up to 8000 MT/s
- DDR5 RDIMM Memory Speeds Up to 12, 800 MT/s
- Support for RDIMM, 3DS RDIMM, MRDIMM, and Tall DIMM
- Up to 128 PCIe Gen 6 + 16 PCIe Gen 4 Lanes on 2P Platform
- Up to 96 PCIe Gen 6 + 8 PCIe Gen 4 Lanes on 1P Platform
Key Features of the AMD SP8 Platform
In contrast, the SP8 platform aims to deliver a robust entry-level solution while still supporting EPYC Verano chips. It maintains compatibility with similarly impressive memory capabilities but is optimized for 8-channel configurations. Interestingly, SP8 enhances the number of Gen 6.0 lanes to provide up to 192 PCIe Gen 6.0 lanes on dual-socket setups and 128 lanes on single-socket configurations.
In summary, the AMD SP8 platform includes:
- Up to 8-Channel DDR5 Support
- DDR5 ECC Memory Speeds Up to 8000 MT/s
- DDR5 RDIMM Memory Speeds Up to 12, 800 MT/s
- Support for RDIMM, 3DS RDIMM, MRDIMM, and Tall DIMM
- Up to 192 PCIe Gen 6 + 16 PCIe Gen 4 Lanes on 2P Platform
- Up to 128 PCIe Gen 6 + 8 PCIe Gen 4 Lanes on 1P Platform
The AMD EPYC Venice processors, featuring either Zen 6C or Zen 6 Dense configurations, will support up to 32 cores per Chiplet (CCD) across a total of eight CCDs, culminating in an impressive peak of 256 cores. Each CCD will include 128 MB of L3 cache, resulting in a cumulative total of 1 GB of cache across the entire chip.
Furthermore, the architecture incorporates dual I/O dies that boast PCIe Gen 6.0 and CXL 3.1 capabilities along with DDR5-8000 memory support, confirming AMD’s continued innovation in the data center space.
AMD’s standard EPYC Venice and Verano CPUs, built on Zen 6 cores, will feature up to 12 cores per CCD, leveraging the same dual I/O die architecture. The resultant configurations could yield up to 96 cores and 192 threads, comparable to current Turin offerings, while boasting a bandwidth-efficient cache size of 48 MB per CCD—signifying a 50% increase from the previous generation Zen 5’s 32 MB L3 cache.
- EPYC 9006 “Venice”with Zen 6C: 256 Cores / 512 Threads / Up To 8 CCDs / 1024 MB L3 Cache
- EPYC 9005 “Turin”with Zen 5C: 192 Cores / 384 Threads / Up To 12 CCDs / 384 MB L3 Cache
- EPYC 9006 “Venice”with Zen 5: 96 Cores / 192 Threads / Up To 8 CCDs / 384 MB L3 Cache
- EPYC 9005 “Turin”with Zen 5: 96 Cores / 192 Threads / Up To 16 CCDs / 384 MB L3 Cache
Notably, reports indicate that EPYC SP7 chips will feature a thermal design power (TDP) of around 600W, an increase from the 400W seen in Zen 5 models, while SP8 variants are expected to operate within a TDP range of 350-400W. AMD is clearly committed to enhancing cores, compute capabilities, and I/O performance, setting the stage for advanced data center solutions with the upcoming Venice and Verano CPUs.
As the launch dates for these impressive processors approach, excitement builds around the enhancements they will bring to the data center segment.
News Source: @Olrak29_
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