Broadcom Launches Innovative 3.5D XDSiP Technology Featuring Four Compute Tiles and 12 HBM Sites in One Package

Broadcom has recently introduced its innovative 3.5D eXtreme Dimension System in Package (XDSiP) technology, aimed at revolutionizing custom computing platforms with improved performance and efficiency.

Revolutionizing AI and HPC with Broadcom’s 3.5D XDSiP Platform

Press Release: Today, Broadcom Inc. officially launched its 3.5D XDSiP platform technology, empowering consumer AI sectors to design advanced custom accelerators known as XPUs. This cutting-edge platform integrates over 6000 mm² of silicon and accommodates up to 12 high-bandwidth memory (HBM) stacks within a single packaged device, making it possible to achieve low-power, high-efficiency computing tailored for large-scale AI applications. Notably, Broadcom has achieved a groundbreaking advance by unveiling the industry’s first Face-to-Face (F2F) 3.5D XPU.

As the demand for training generative AI models surges, the need for expansive clusters comprising between 100,000 to a million XPUs intensifies. This escalating need challenges traditional computing architectures, as the integration of advanced compute capabilities, memory, and I/O resources becomes vital for attaining desired performance levels while keeping energy consumption and costs in check. Existing paradigms, such as Moore’s Law and traditional process scaling methods, no longer suffice to meet these rigorous demands. Hence, the evolution towards sophisticated system-in-package (SiP) integration emerges as essential for developing the next generation of XPUs.

Over the past decade, 2.5D integration, which allows for the combination of several chiplets measuring up to 2500 mm² along with HBM modules up to 8 stacks positioned on an interposer, has significantly benefited XPU development. However, with the introduction of more intricate large language models (LLMs), their training processes demand advanced 3D silicon stacking solutions that optimize size, power consumption, and cost, leading to a growing preference for 3.5D integration. This approach amalgamates 2.5D packaging with 3D silicon stacking, making it the likely leading technology for XPUs in the decade ahead.

Broadcom’s 3.5D XDSiP platform boasts remarkable enhancements in interconnect density and energy efficiency when compared to conventional Face-to-Back (F2B) methods. Through innovative F2F stacking, which connects the top metal layers of both the upper and lower dies, this technology ensures a dense, reliable connection with minimal electrical interference and unparalleled mechanical durability. Furthermore, Broadcom’s platform includes intellectual property (IP) and proprietary design workflows that facilitate efficient and correct integration of 3D die stacking for optimal power, clock, and signal connections.

Key Advantages of Broadcom’s 3.5D XDSiP Technology

Enhanced Interconnect Density: Achieves a remarkable 7x increase in signal density between stacked dies compared to conventional F2B technologies.
Superior Power Efficiency: Delivers a 10x decrease in power usage for die-to-die interfaces using 3D HCB technology instead of planar alternatives.
Reduced Latency: Minimizes latency for data transfer between compute, memory, and I/O components within the 3D architecture.
Compact Form Factor: Allows for smaller interposers and packaging, resulting in cost efficiency and decreased package warpage.

Broadcom’s pioneering F2F 3.5D XPU integrates four compute dies, one I/O die, and six HBM modules, exploiting TSMC’s state-of-the-art processing nodes and advanced 2.5D CoWoS packaging technologies. The company’s proprietary design methodologies prioritize automation, leveraging industry-standard tools to ensure successful implementation even amidst the complexity of the chip.

The 3.5D XDSiP has successfully demonstrated comprehensive functionality and notable performance across crucial IP components such as high-speed SerDes, HBM memory interfaces, and die-to-die interconnects. This achievement illustrates Broadcom’s profound expertise in designing and testing complex integrated circuits within the 3.5D framework.

TSMC and Broadcom have formed a synergistic partnership over recent years, uniting TSMC’s cutting-edge logic processes and 3D chip stacking innovations with Broadcom’s design proficiency.

We are excited about the prospects of productizing this platform to spur AI advancements and facilitate future progress in the industry.

– Dr. Kevin Zhang, Sr. VP of Business Development & Global Sales, Deputy Co-COO, TSMC

With a pipeline of over five 3.5D products currently in development, a growing number of Broadcom’s consumer AI clients are set to adopt the 3.5D XDSiP technology, with production shipments anticipated to commence in February 2026. For further insights into Broadcom’s innovative 3.5D custom compute platform, click here.