AMD Shifts from SERDES to “Sea-of-Wires” D2D Interconnect in Upcoming Zen 6 CPUs for Enhanced Power Efficiency and Reduced Latency

AMD is set to revolutionize its processor architecture with innovative die-to-die (D2D) interconnect technology in its forthcoming Zen 6 CPUs. Preliminary insights into this advancement have already surfaced through the Strix Halo APUs.

AMD’s Interconnect Innovations as Highlighted by Strix Halo APUs

Prior to delving into the intricacies, it’s commendable to recognize the investigative efforts by High Yield in unveiling the D2D interconnect modifications in Strix Halo. This breakthrough is a promising indicator of what lies ahead for AMD. For years, AMD has utilized the same die-to-die interconnect technology since the launch of Zen 2. However, the upcoming Zen 6 processors showcase a significant evolution, with elements of what is being dubbed as ‘Zen 6 DNA’ already present in the Strix Halo APUs.

Understanding AMD’s Current D2D Communication

AMD’s existing interconnect technology relies on Serial-Deserializer (SERDES) physical layers positioned on the edges of the chiplet complex dies. This method facilitates high-speed communication through serial lanes that transmit data across the organic substrate to the input/output and system-on-chip (SoC) die. SERDES serves as a bridge, converting parallel data streams from different chiplet complex dies into serial bitstreams, which are then relayed across the package. The traditional method of using hundreds of copper wires to connect dies is not feasible with conventional substrates.

Technical diagram of AMD Ryzen AI Max PRO 395 showing chip and die cross-sections. — Image Credits: AMD/High Yield

Conversely, the deserializer on the opposite end converts the serial bitstreams back to their original format. While this SERDES mechanism has served its purpose, it does introduce inefficiencies: the energy overhead for serialization and deserialization processes necessitates resources for clock recovery, equalization, and data encoding/decoding. This method also incurs additional latency, impacting the overall performance of D2D communication.

The Need for Enhanced D2D Communication

The SERDES methodology was adequate when D2D communication was limited to certain standard dies. However, with the increasing integration of neural processing units (NPUs), the demand for consistent, low-latency bandwidth to memory and chiplet complex dies is escalating. The Strix Halo architecture signifies a pivotal transformation in how AMD’s Zen 6 dies will engage with one another, employing TSMC’s Integrated Fan-Out on Substrate (InFO-oS) alongside a Redistribution Layer (RDL).We will explore these technologies in greater detail.

Microchip design showcasing CCD and next-generation die-to-die interconnect. — Image Credits: High Yield

Innovations in D2D Interconnect Technology

To alleviate the inefficiencies associated with traditional D2D communication, AMD has implemented a novel design in Strix Halo. It utilizes multiple short, parallel wires positioned in an interposer beneath the dies crafted from RDL. This approach establishes a network of connections between the silicon dies and the organic substrate, enhancing communication capabilities across wider parallel ports. High Yield’s analysis indicates that the Strix Halo design features a distinctive array of small pads reminiscent of classic ‘fan out’ layouts, effectively replacing the bulky SERDES system.

Microchip illustration showing Logic chips and substrate structure. — Image Credits: TSMC

Benefits and Challenges of the Fan-Out Approach

This updated D2D interconnect method is set to reduce power consumption and latency significantly as it eliminates the need for serialization/deserialization. Moreover, the overall bandwidth can be increased thanks to the incorporation of additional ports across the CPU architecture. Despite these advancements, employing a fan-out design does come with challenges, notably concerning the intricacies involved in managing multi-layer RDL and adapting to new routing priorities, as the space beneath the dies is consumed by fan-out wiring.

All in all, AMD’s introduction of the Strix Halo technology marks a remarkable advancement in D2D interconnects, and it is anticipated that this innovative approach will carry over into the Zen 6 CPUs. The insights revealed by High Yield are indeed noteworthy, inviting tech enthusiasts to delve deeper into these groundbreaking developments.

https://www.youtube.com/watch?v=maH6KZ0YkXU

How AMD is re-thinking Chiplet Design (https://www.youtube.com/watch?v=maH6KZ0YkXU)

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