AMD Launches Next-Gen EPYC Venice “Zen 6” CPUs Featuring 256 Cores in 2026, Plus EPYC Verano CPUs & Instinct MI500 GPUs Coming in 2027

AMD has officially unveiled its upcoming product lineups featuring the next-generation EPYC and Instinct family of processors, which include the Zen 6-based EPYC Venice, EPYC Verano, and the Instinct MI500 series.

AMD’s Next-Gen Offerings: EPYC Venice, EPYC Verano, and Instinct MI500 Series Unveiled

In a recent keynote focused on advancing AI technologies, AMD presented exciting details about its forthcoming EPYC and Instinct platforms. Anticipated for release next year, the Instinct MI400 series promises a substantial performance enhancement, boasting a 10x increase over the currently available MI350 series.

In terms of the EPYC Venice lineup, expected to debut in 2026, it will integrate the newly developed Zen 6 architecture and offer configurations that include up to 256 cores, indicative of AMD’s ongoing commitment to high-performance computing.

As per earlier reports, the sixth generation of EPYC Venice CPUs will feature two distinct variations—similar to the existing Zen 5 and Zen 4 models. This includes a standard Zen 6 variant alongside a denser Zen 6C variant. These chips will utilize SP7 and SP8 socket designs, where SP7 caters to high-end solutions, while SP8 is tailored for entry-level server applications. Furthermore, they will support both 12-channel and 16-channel memory configurations.

Regarding performance specifications, the AMD EPYC 9006 series, dubbed “Venice, ”will feature processors built with up to 96 cores and 192 threads utilizing 8 CCDs. On the other hand, the Zen 6C versions are projected to support up to 256 cores and 512 threads, enhancing their processing capabilities significantly.

EPYC 9006 “Venice”With Zen 6C: 256 Cores / 512 Threads / Up To 8 CCDs
EPYC 9005 “Turin”With Zen 5C: 192 Cores / 384 Threads / Up To 12 CCDs
EPYC 9006 “Venice”With Zen 5: 96 Cores / 192 Threads / Up To 8 CCDs
EPYC 9005 “Turin”With Zen 5: 96 Cores / 192 Threads / Up To 16 CCDs

The new chips are set to be manufactured using TSMC’s advanced 2nm process, delivering potentially double the CPU-to-GPU bandwidth, alongside an impressive 70% generation-on-generation performance gain and support for up to 1.6 TB/s memory bandwidth. The complete suite of AMD EPYC Venice processors, as well as the Instinct MI400 series and Vulcano FPGAs, will be integrated into the Helios data center rack by 2026.

Looking to the future, AMD is poised to introduce its next-generation EPYC Verano CPUs and the Instinct MI500 series in 2027. The Verano series is expected to leverage either an improved version of the Zen 6 architecture or transition to the next-gen Zen 7 architecture. AMD’s new strategy promotes an annual release cadence, thus facilitating rapid iteration in the data center and AI sectors, echoing NVIDIA’s dual-offering approach of standard and “Ultra”models. This will lead to groundbreaking advances in performance for next-gen AI infrastructure.

Overview of the AMD EPYC CPU Families

Family Name	AMD EPYC Summer	AMD EPYC Venice	AMD EPYC Turin-X	AMD EPYC Turin-Dense	AMD EPYC Turin	AMD EPYC Siena	AMD EPYC Bergamo	AMD EPYC Genoa-X	AMD EPYC Genoa	AMD EPYC Milan-X	AMD EPYC Milan	AMD EPYC Rome	AMD EPYC Naples
Family Branding	EPYC 9007	EPYC 9006	EPYC 9005	EPYC 9005	EPYC 9005	EPYC 8004	EPYC 9004	EPYC 9004	EPYC 9004	EPYC 7004	EPYC 7003	EPYC 7002	EPYC 7001
Family Launch	2027	2026	2025	2025	2024	2023	2023	2023	2022	2022	2021	2019	2017
CPU Architecture	It was 7	It was 6	It was 5	Zen 5C	It was 5	It was 4	It was 4C.	Zen 4 V-Cache	It was 4	It was 3	It was 3	It was 2	It was 1
Process Node	TBD	2nm TSMC	4nm TSMC	3nm TSMC	4nm TSMC	5nm TSMC	4nm TSMC	5nm TSMC	5nm TSMC	7nm TSMC	7nm TSMC	7nm TSMC	14nm GloFo
Platform Name	TBD	SP7	SP5	SP5	SP5	SP6	SP5	SP5	SP5	SP3	SP3	SP3	SP3
Socket	TBD	TBD	LGA 6096 (SP5)	LGA 6096 (SP5)	LGA 6096	LGA 4844	LGA 6096	LGA 6096	LGA 6096	LGA 4094	LGA 4094	LGA 4094	LGA 4094
Max Core Count	TBD	96	128	192	128	64	128	96	96	64	64	64	32
Max Thread Count	TBD	192	256	384	256	128	256	192	192	128	128	128	64
Max L3 Cache	TBD	TBD	1536 MB	384 MB	384 MB	256 MB	256 MB	1152 MB	384 MB	768 MB	256 MB	256 MB	64 MB
Chiplet Design	TBD	8 CCD’s (1 CCX per CCD) + 2 IOD?	16 CCD’s (1CCX per CCD) + 1 IOD	12 CCD’s (1CCX per CCD) + 1 IOD	16 CCD’s (1CCX per CCD) + 1 IOD	8 CCD’s (1CCX per CCD) + 1 IOD	12 CCD’s (1 CCX per CCD) + 1 IOD	12 CCD’s (1 CCX per CCD) + 1 IOD	12 CCD’s (1 CCX per CCD) + 1 IOD	8 CCD’s (1 CCX per CCD) + 1 IOD	8 CCD’s (1 CCX per CCD) + 1 IOD	8 CCD’s (2 CCX’s per CCD) + 1 IOD	4 CCDs (2 CCXs per CCD)
Memory Support	TBD	DDR5-XXXX?	DDR5-6000?	DDR5-6400	DDR5-6400	DDR5-5200	DDR5-5600	DDR5-4800	DDR5-4800	DDR4-3200	DDR4-3200	DDR4-3200	DDR4-2666
Memory Channels	TBD	16-Channel (SP7)	12 Channel (SP5)	12 Channel	12 Channel	6-Channel	12 Channel	12 Channel	12 Channel	8 Channel	8 Channel	8 Channel	8 Channel
PCIe Gen Support	TBD	TBD	TBD	128 PCIe Gen 5	128 PCIe Gen 5	96 Gen 5	128 Gen 5	128 Gen 5	128 Gen 5	128 Gen 4	128 Gen 4	128 Gen 4	64 Gen 3
TDP (Max)	TBD	~600W	500W (cTDP 600W)	500W (cTDP 450-500W)	400W (cTDP 320-400W)	70-225W	320W (cTDP 400W)	400W	400W	280W	280W	280W	200W