AMD Denies 3D V-Cache on All CCDs for Ryzen X3D CPUs Due to Economic Factors

With the recent unveiling of AMD’s innovative 3D V-Cache CPUs, a pressing question arose: why hasn’t Team Red opted to implement additional cache across all Core Chiplet Dies (CCDs)? The company has now clarified this strategic decision.

AMD Explains the Financial Implications of Dual CCD 3D V-Cache

For those who may not know, AMD has introduced its latest Zen 5 3D V-Cache processors, including the Ryzen 9 9950X3D and Ryzen 9 9900X3D models, which feature a dual CCD architecture. Although AMD has made significant strides in performance enhancement with this new architecture, the 3D V-Cache is limited to just one of the CCDs. The potential to harness the cache capabilities on both chiplets could theoretically boost performance, but there’s more to this story. According to HardwareLuxx, AMD offered insights on this matter:

We asked AMD if there were any technical reasons why we haven’t seen a Ryzen processor with two CCDs and a 3D V-Cache on each of the CCDs. The answer was surprising: there are no technical reasons or challenges.

Such a processor would simply be too expensive, and games would not benefit from a second CCD with a 3D V-Cache to the same extent as they would from the step from 32 to 96 MB L3 cache for one CCD.

– AMD via HardwareLuxx

This statement reveals that the decision not to implement a dual 3D V-Cache system is not technical in nature but rather influenced by economic factors. Moreover, AMD indicated that utilizing a dual 3D V-Cache could complicate thread scheduling. Optimal performance depends on keeping threads confined to the cores with the 3D V-Cache. When threads move across both CCDs, the performance advantage dwindles.

Interestingly, AMD acknowledged that it had previously tested a processor featuring dual 3D V-Cache but ultimately decided against making it available to consumers. However, this does not rule out the possibility of such CPUs being offered in the future, particularly for specialized applications where the cost of development can be justified by the performance gains achieved.

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